FIG. 19A is a diagram schematically illustrating a typical configuration of a logic LSI chip. In order to raise the throughput of data processing in a logic LSI chip (LOGIC) in FIG. 19A, a pipeline operation is performed in which the path from a data input (DIN) to a data output (DOUT) is divided into a plurality of logic circuit blocks (LGK) at flip-flops (FF) and the flip-flops (FF1, FF2, and FF3) are controlled by a clock (CK). In the logic LSI chip (LOGIC), it is possible to perform the division in such a manner that each of the logic circuit blocks (LGK) will have substantially the same delay. As a result, operating frequency can be raised by performing a pipeline operation using flip-flops (FF1, FF2, and FF3) controlled by the common clock as set forth above. In the pipeline operation, a flip-flop (FF) samples the output of the immediately preceding logic circuit block (LGK) in synchronization with the clock and provides the sampled value to the succeeding logic circuit block (LGK), and the operation performed by each logic circuit block (LGK) is carried out in one clock cycle.
FIG. 19B is a diagram useful in describing a typical configuration of a clock-synchronized synchronous DRAM (SDRAM). For the sake of simplicity in FIG. 19B, input-stage flip-flops that sample respective ones of a command (CMD) and an address (ADD) are represented by FF1, and a command decoder and an address decoder are represented by a decoder (DEC). In the synchronous DRAM (SDRAM) shown in FIG. 19B, flip-flops FF1 and FF4 of input and output stages, respectively, of the command and address are controlled by clock CK (the rising edge of the clock). Other flip-flops (e.g., FF2, FF3) in the chip are controlled by timing signals produced in a timing control circuit (TG) by generating pulses in a pulse generator (PG) from the clock (CK) that has entered from an external terminal and delaying the pulses by analog delay circuits (ADLY1, ADLY2).
In the synchronous DRAM, the delays of the decoder (DEC), a memory array (MEMCORE) and a data bus (DB), which are functional blocks within the chip, differ greatly from one another. If timing is controlled by the common clock, the clock frequency at which operation is possible is decided by the delay of the memory array. That is, in the synchronous DRAM, the delays of the function blocks cannot be made approximately the same, pipeline operation cannot be carried out using flip-flops (FF) controlled by the common clock and, as a result, it is difficult to raise the frequency, as in the logic LSI of FIG. 19A.
The operation of the synchronous DRAM illustrated in FIG. 19B will be described taking a read operation as an example. When a command (CMD) and address (ADD) are supplied to the synchronous DRAM, each of these is captured into the chip in synchronization with the clock (CK) by the corresponding input-stage flip-flop FF1. The command and address that have been captured in the flip-flop FF1 are decoded by the decoder (DEC), and the operation (read in this case) and the address to be selected are decided. A clock pulse from the pulse generator (PG) is supplied to the clock terminal CK of the next flip-flop FF2 upon being delayed by the analog delay (ADLY1) so as to match with this timing, and a main word line (MWLB) of the selected address is activated in the memory array (MEMCORE).
Next, the pulse that has been delayed by the analog delay (ADLY1) is supplied to the clock terminal CK of the flip-flop FF3 upon being further delayed by the analog delay (ADLY2) so as to match with the timing at which a signal is generated on a bit line (not shown) from a memory cell (not shown) selected in the memory array (MEMCORE), a sense-amplifier start-up signal (SAN) is activated and the generated signal is amplified by a sense amplifier (not shown).
When a read command is input in succession, the signal that has been amplified by the sense amplifier (not shown) is transmitted up to an output buffer through a data bus (DB) and is output from the external data output terminal (DOUT) of the chip in synchronization with the clock from a counter (COUNT).
Patent Document 1 describes an arrangement having a coarse adjustment circuit for coarsely adjusting clock phase and a fine adjustment circuit for finely adjusting clock phase. It should be noted that the invention described in Patent Document 1 has an arrangement that is completely different from that of the present invention, described later. Further, Patent Document 2 discloses a timing generating circuit having first and second DLLs (Delay Locked Loops) for supplying supply voltage to serially connected coarse and fine delay units, wherein delay units used as monitor circuits of the first and second DLLs have the same circuit configurations as those of the coarse and fine delay units, respectively.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2004-110490
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2006-186547
[Non-Patent Document 1] Kohtaroh Gotoh, Shigetoshi Wakayama, Miyoshi Saito, Junji Ogawa, Hirotaka Tamura, Yoshinori Okajima and Masao Taguchi, “All-Digital Multi-Phase Delay Locked Loop for Internal Timing Generation in Embedded and/or High-Speed DRAMs”, 1997 Symposium on VLSI Circuits Digest of Technical Papers (pp. 107-108)